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1 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b S3051 ? 2.5 gbps limiting amplifier device specification features ? 2 ghz bandwidth ? 32db gain ? single +5v power supply ? fully differential architecture ? 16 pin glass-metal package applications ? sonet oc-48 ? fiber optic data links ? high-speed fm limiting amplifier figure 1. system block diagram din- din+ dout+ dout input out out+ S3051 v +ref v ?ef v cc c byp c in c in c byp general description the S3051 limiting amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber optic receivers with data rates up to 2.5 gbps. the amplifier's gain is 32db, and differential signals as small as 12 mvp-p, can be amplified to 900 mvp-p. figure 1 shows a typical system application.
2 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b detailed description the S3051 is an integrated limiting amplifier in- tended for high-frequency fiber-optic applications. the circuit connects to typical transimpedance am- plifiers found within a fiber-optic link. the linear signal output from a transimpedance amplifier can contain significant amounts of noise, and may vary in amplitude over time. the S3051 limiting amplifier quantizes the signal, and outputs a voltage limited waveform over a 38 db input dynamic range. at low signal levels, below 12 mvp-p, the circuit be- haves as a linear amplifier. at higher levels the device becomes a limiting amplifier. figure 2. functional block diagram dout dout+ din din+ v ref v + ref 50 11 10 9 8765 4 3 12 2 1 16 15 14 13 nc vcc(ob) vcc(gs1,ss2) gnd(ob) gnd(ob) gnd(ob) gnd(ob) gnd(gs1,gs2) gnd(gs1,gs2) 5k 5k vcc(gs1,gs2) v cc = +5v gs1 gs2 ob 110pf 110pf nc ..... no connect 50 5k 5k the referred wideband input noise (160 m vrms) al- lows for a less than 1e-9 bit error rate for inputs down to 2 mvp-p. the S3051 is designed to allow adjustment of the dc offset between the din+ and dinC inputs. v +ref can be used as a reference from which the required offset can be subtracted to set the dc bias level at dinC. similarly, v Cref can be used to set the dc bias level at din+. (see application information). if no adjustment is made to the input dc bias level, two resistors can be connected in a negative feed- back configuration in order to cancel any dc offset at the input. this will minimize the pulse width distor- tion. (see separate S3051 limiting amplifier application document.)
3 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b table 1. S3051 pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d + t u o dg o l a n ao2 . t u p t u o a t a d e v i t i s o p C t u o dg o l a n ao3 . t u p t u o a t a d e v i t a g e n v f e r C c do9 g n i s s a p y b l a n r e t x e e s o l c - p u s e r i u q e r . e c n e r e f e r e v i t a g e n a t a d g n i l p u o c t u p n i e h t g n i h c t a m , r e t a e r g r o , f 7 4 0 . 0 r o t i c a p a c a h t i w ) . 7 e r u g i f e e s ( . r o t i c a p a c C n i dg o l a n ai0 1. t u p n i a t a d e v i t a g e n + n i dg o l a n ai1 1. t u p n i a t a d e v i t i s o p v f e r + c do 2 1g n i s s a p y b l a n r e t x e e s o l c - p u s e r i u q e r . e c n e r e f e r e v i t i s o p a t a d g n i l p u o c t u p n i e h t g n i h c t a m , r e t a e r g r o , f 7 4 0 . 0 r o t i c a p a c a h t i w ) . 7 e r u g i f e e s ( . r o t i c a p a c c c vv 5 +s 4 1 , 3 1 , 7. y l p p u s e v i t i s o p d n gv os , 6 , 5 , 4 , 1 6 1 , 5 1 . y l p p u s e v i t a g e n c n8. t c e n n o c o n
4 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b figure 3. S3051 16-pin glass-metal package e c i v e dr e w o p x a m q a j 1 5 0 3 sw m 0 5 7w / c ? 0 6 thermal management
5 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b figure 4. S3051 pinout (top view) S3051 top view 16 lead flat pack 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 gnd dout+ dout gnd gnd gnd vcc nc din+ v +ref din- v ?ef gnd gnd vcc vcc
6 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b r e t e m a r a pn i mp y tx a ms t i n u e g n a r e r u t a r e p m e t e g a r o t s5 5 C5 7 1 +c ? e r u t a r e p m e t g n i s s e c o r p0 0 4 +c ? v y l p p u s r e w o p c c d n g o t t c e p s e r h t i w0 . 6v ) C n i d , + n i d ( e g a t l o v t u p n i0 . 6v 0 5 h t i w ( C t u o d , + t u o d w ) d a o l5 . 2 v c c 3 . 0 + v y t i v i t i s n e s d s e 1 0 0 5 r e d n uv table 2. recommended operating conditions table 3. absolute maximum ratings r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a0 4 C5 8 +c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j0 1 C0 3 1 +c ? v n o e g a t l o v c c d n g o t t c e p s e r h t i w5 7 . 40 . 55 2 . 5v 1. human body model.
7 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b table 4. ac electrical characteristics (v cc = 5v 5%, t a = C40?c to +85?c) s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v d i = v ( + n i v ( - ) C n i ) e g n a r e g a t l o v ) d e t i m i l s i t u p t u o h c i h w r e v o ( 2 10 0 0 1p - p v m , k a e p - o t - k a e p l a i t n e r e f f i d ) . 5 e r u g i f e e s ( a d n i a g l a i t n e r e f f i d2 38 4b dv d i p - p v m 8 = v n e s i o n t u p n i l a i t n e r e f f i d 0 6 1 8 5 . 3 v v n/ ? hz = e s i o n d e r r e f e r t u p n i w o l / e s i o n t u p t u o s m r , n i a g y c n e u q e r f z h g 2 C z h k 7 d w pn o i t r o t s i d h t d i w e s l u p1 . 0i u s p b g 8 8 4 . 2 s i t u p n i 2 3 2 v , s b r p 1 - d i = d n a p - p v m 2 1 1 e t o n p - p v m 0 0 0 1 t r t , f ) % 0 8 C % 0 2 ( d e e p s e g d e t u p t u o0 0 15 6 1s pv d i p - p v m 2 1 = v d o = v ( + t u o v ( - ) C t u o ) g n i w s e g a t l o v t u p t u o l a i t n e r e f f i d0 5 50 0 9p p v m , k a e p - o t - k a e p 0 5 , l a i t n e r e f f i d w e n i l . n o i t a n i m r e t ) . 6 e r u g i f e e s ( w b h h t d i w d n a b l a n g i s - l l a m s r e p p u6 . 12 z h g w b l f f o - t u c y c n e u q e r f w o l2z h k d n a g n i l p u o c t u p n i n i s a g n i s s a p y b . 7 e r u g i f 1 1 st n e i c i f f e o c n o i t c e l f e r t u p n i5 1 Cb d 0 5 , z h g 2 C z h k 0 0 2 w . n o i t a n i m r e t e n i l 2 1 sn o i t a l o s i5 4 Cb d 0 5 , z h g 2 C z h k 0 0 2 w . n o i t a n i m r e t e n i l 2 2 st n e c i f f e o c n o i t c e l f e r t u p t u o5 1 Cb d 0 5 , z h g 2 C z h k 0 0 2 w . n o i t a n i m r e t e n i l note 1. input offset calibrated out at v id = 15mv.
8 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us t n e m m o c i c c t n e r r u c y l p p u s r e w o p5 70 0 1a m v n i d e g a t l o v s a i b t u p n iv c c 2 /v v t e s f f o t e s f f o ) C n i d , + n i d ( t u p n i m u m i x i m t s u j d a v n i d 0 0 3 v m v l o e g a t l o v w o l t u p t u o v c c 5 9 . 0 C v c c 5 . 0 C v v h o e g a t l o v h g i h t u p t u o v c c 5 . 0 C v c c v table 5. dc electrical characteristics (v cc = 5v 5%, t a = C40?c to +85?c) figure 5. input voltage vin+ vin vid = [v in+ ] - [v in ] 5mv min 500mv max 10mv min 1000mv max 0 figure 6. output voltage v out+ v out v od = [v out+ ] - [v out ] 300mv min 600mv min 0
9 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b applications information connecting to the input of S3051 the equivalent input circuit of S3051 is shown in figure 7. both dc biasing and 50 ohm input line termination have been implemented internally. figure 7. S3051 equivalent input circuit v cc v cc din- din+ v in+ v in 110pf 110pf 0.047 f 0.047 f 0.047 f 0.047 f 9 10 11 12 5 k 50 50 5 5 v ?ef v ?ef 5 k 5 k 5 k
10 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b connecting to the output of S3051 the output of the S3051 does not require any external termination. figure 8. output termination 0.1 f 0.1 f 5v 100 +5v v cc ?.4v v cc ?.4v s3050 S3051 dout+ dout- 2 3 19 18 zo=50 zo=50 v in+ v offset din+ v -ref din- v +ref dout+ dout- c byp c byp + - v offset din+ v -ref din- v +ref c byp dout+ dout- v in- c byp + - figure 9. adjusting the dc bias level at dinC figure 10. adjusting the dc bias level at din+ adjusting input dc offset the dc bias level at dinC and din+ can be adjusted by inserting a difference amplifier function, as shown in figures 9 and 10.
11 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b typical operating characteristics figure 11. vcc supply current vs. temperature figure 12. frequency response
12 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b figure 13. eye pattern @v id = 12mv figure 14. eye pattern @v id = 1000mv
13 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b figure 15. input voltage vs. output voltage
14 S3051 2.5 gbps limiting amplifier july 14, 1999 / revision b x xxxx x prefix device package amcc is a registered trademark of applied micro circuits corporation. copyright ? 1999 applied micro circuits corporation amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i C s1 5 0 3k c a p t a l f d a e l 6 1 C a ordering information

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